A simplified network illustrating a computing system is seen in FIG. 3A which shows the basic elements of a central processing module (CPM) 10, a Main Memory Module 40 and an Input/Output Module 50. These modules are interconnected via a dual system bus structure designated as having two system busses 22a and 22b. These busses are interchangeable system busses and provide parallel redundant transfer paths.
The network of FIG. 3A is seen enhanced with the addition of a Maintenance Subsystem Module 60 which is shown in FIG. 3B. The Maintenance Subsystem Module 60 provides both diagnostic functions to all of the modules in the network but is also required to initialize all the system modules and to "start-up" the system for operation. In FIG. 3B, the Maintenance Subsystem 60 is shown connecting to all of the system modules by means of a dashed line series of connections 64a, 64b and 64c. These connections represent the basic maintenance connections of a JTAG integrity system such as is specified in IEEE 1149.1. The IEEE 1149.1 specification describes an industry standardized type of interface which provides a bit-serial data transfer between the various targeted modules of the network and the Maintenance Subsystem 60.
All the various system modules in the network are setup or "initialized" for system operation through the bit-serial interface lines 64a, 64b, and 64c. This type of interface is a system compromise between cost and performance. It is inexpensive cost-wise, since it is standard and only uses a few wires and since it is a bit-serial data transfer operation.
However, the bit-serial aspect of data transfer also makes it a very slow operation when massive amounts of information must be transferred. However, in many systems this is tolerable because the system initialization does not require an excessive amount of data transfer to most of the interconnecting modules in a network.
In the architecture of FIG. 3B, the case is presented where inordinate and significant time periods are wasted when initialization is effectuated by only using the standard JTAG interface, especially when it is desired to transfer "channel microcode" instructions for the I/O module 50.
One type of central processing module 10 is shown in FIG. 2 connected to a Maintenance Subsystem 60. The Maintenance Subsystem 60 includes a maintenance processor 64 with several peripheral units attached, such as cartridge tapes 61, hard disk 62, and floppy disk 63. These devices can be used to provide the large database information that may be necessary to set-up the system for operation. The serial interface between the Maintenance Subsystem 60 and the central processing module 10 (CPM) is shown on bus lines 60si which connect the maintenance processor 64 from the maintenance subsystem over to the maintenance controller 12 of the CPM module 10.
Also seen in FIG. 2 are the major elements of the processor logic in the CPM 10. These include the processor 14, the Data Path Array 20, the Control PAL 16 and the microcode RAM 18 which holds the instruction codes for the processor 14. It will be seen that the processor 14 can access the major system modules 40 and 50 via the system busses 22a and 22b through the on-card Data Path Array 20. The Data Path Array converts from the on-card high speed processor bus 14b over to the slower inter-module system busses 22a and 22b. The soft, flexible Control PALs 16 is used to provide control of these busses and also the data path array operations.
In FIG. 2, the dashed lines are used to show the on-card versions of the serial JTAG connections which are indicated as 12p, 12c and 12d. Once initialization of a system has been completed in FIG. 2, these JTAG connection lines are no longer essentially used.
Another view of the computer network is illustrated in FIG. 3C where the Input/Output Module 50 is seen to have a dedicated unit for Channel Adapters 50ca and where the main system memory module 40 is seen to have a dedicated section 40cm. for holding the channel microcode designated 40cm. The Input/Output Modules 50 connect to various peripherals and are under control of the Channel Adapters 50ca which provide the appropriate protocol and timing for communication purposes.
The channel microcode unit 40cm of FIG. 3C is a dedicated repository for channel microcode instructions which enables the Channel Adapters 50ca of the Input/Output Module 50 to control and communicate data transfers between I/O module 50 and the peripherals 70.
For efficiency of design and of production, it is most desirable to make as few types of unique hardware units as possible, that is to say, it is optimum to use identical hardware to accomplish many different tasks. Thus, the I/O module 50, although it must interface with many different types of peripheral devices 70 (for example, SCSI disks, tapes, printers, etc.) may optimally use identical or very similar hardware to accomplish this. Each type I/O device (peripheral) is interfaced with its own individual Channel Adapter 50ca. These channel adapters which are used are essentially identical hardware. Then to allow each adapter to properly interface to the different peripheral units, there is required device protocols, there is required a unique "driver" software using the "channel microcode" to run each of the channel adapters 50ca.
At the original system initialization time period, the Maintenance Subsystem 60 is sensitive to the system I/O device configurations and connections. Because of this, it must load the appropriate "channel microcode" into the appropriate locations in Main Memory 40, shown as unit area 40cm in FIG. 3C. When the I/O module 50 is initialized and running, it will then access the appropriate devices "channel microcode" from the unit 40cm of the main system memory 40, and then bring this into the Channel Adapters 50ca for normal system operation.
The power of having "soft" microcode routines is useful in that somewhat standardized I/O hardware can be used to implement numerous varied types of I/O device connectivity. This flexibility comes at the cost of having to load up (Write) the channel microcode into the dedicated channel microcode unit 40cm of Main Memory 40 and this must be done each time that the system is initialized.
Now, such systems, as indicated in FIG. 3C, are essentially shown in loading the channel microcode since it was normally done through the JTAG bus 60si which has various sub-bus lines 64a, 64b, and 64c. The presently described system will be seen to function to eliminate the long time periods necessary to transfer microcode information from the Maintenance Subsystem 60 to the main system memory 40.
Earlier architectures and systems were very inefficient in regard to the loading of channel microcode such as seen in FIG. 3C. If the logic and architecture were implemented only as shown in FIGS. 2 and 3C, then it would still be possible to provide for the necessary writing of channel microcode into Main Memory 40. But however, there would be a quite significant delay, even to the extent of several minutes, for each individual occasion that the system was initialized. Thus, in the systems of FIG. 2 and FIG. 3C, it could be remarked that there were two levels (i) (ii) of inefficiency in regard to the loading up and writing in of channel microcode into the Main Memory Module 40.